1. Field of the Invention
The invention relates to a method for fabricating device structures. More particularly it relates to patterning ceramic layers on areas in a relief structure.
2. Background of the Invention
Economic success in the semiconductor industry is substantially influenced by a further reduction of the minimum feature size that can be produced on a microchip. Reducing the minimum feature size makes it possible to increase the integration density of the electronic components such as transistors or capacitors on the microchip and thus to increase the computing speed of processors and also to increase the storage capacity of memory modules.
In order that the area required by the components on the chip surface is kept small, the depth of the substrate is also utilized in the case of capacitors. To that end, a trench is first introduced into a wafer. Afterward, a bottom electrode is produced, for example, by doping the regions of a wafer adjoining the wall of the trench in order to increase the electrical conductivity. A thin layer of a dielectric is then applied to the bottom electrode. Finally, the trench is filled with an electrically conductive material in order to obtain a counter-electrode. The latter electrode is also referred to as top electrode. This arrangement of electrodes and dielectric means that the capacitor is, as it were, folded. Given electrode areas of constant size, that is to say the same capacitance, the lateral extent of the capacitor on the chip surface can be minimized. Such capacitors are also referred to as “Deep Trench” capacitors.
In memory chips, the charged and discharged states of the capacitor correspond to the two binary states 0 and 1. In order to be able to reliably determine the charge state of the capacitor and thus the information stored in the capacitor, the latter must have a specific minimum capacitance. If the capacitance, or in the case of a partly discharged capacitor, the charge, falls below this value, the signal disappears in the noise and the information about the charge state of the capacitor is lost. After writing, the capacitor is discharged due to leakage currents, which bring about a charge balancing between the two electrodes of the capacitor.
In order to counteract a loss of information through the discharge of the capacitor, in DRAMs the charge state of the capacitor is checked at regular intervals and refreshed as needed, such that a partly discharged capacitor is charged again up to an original state. However, technical limits are imposed on these refreshing times, so that the refresh rate cannot be shortened arbitrarily. During the period of the refreshing time, therefore, the charge of the capacitor is permitted to decrease only to an extent such that reliable determination of the charge state is possible. For a given leakage current, the capacitor must therefore have a specific minimum charge at the beginning of the refreshing time, so that at the end of the refreshing time, the charge state is still high enough above the noise to be able to reliably read out the information stored in the capacitor. With decreasing dimensions of the capacitor, the leakage currents increase, as tunneling effects gain in importance.
In order to be able to ensure a reliable storage of information even with advancing miniaturization, the capacitor must have a sufficient capacitance. In order to obtain the desired high capacitance despite a decreasing structural size, a multiplicity of solution approaches are being pursued. As an example, the surface of the electrodes is provided with a structure whose surface is increased to the extent possible, as the length and width of the electrodes decrease. Furthermore, new materials are being investigated to replace the silicon dioxide, which has been used hitherto as the dielectric, with a higher dielectric constant layer.
In order to achieve a highest possible capacitance for a given size of a capacitor, attempts are being made to dope as highly as possible the region of the semiconductor which directly adjoins the dielectric, in order to produce a highest possible surface charge density in the electrode in direct proximity to the dielectric.
In memory chips, a capacitor is connected to a transistor via which the charge state of the capacitor can be controlled. In deep trench capacitors, the transistor is usually arranged above the capacitor. In order to be able to achieve a sufficient electrical insulation between capacitor and transistor, the topmost section of the trench, which is adjoined by the transistor, is not doped. During the fabrication of the deep trench capacitor, therefore, it is necessary to delimit the region in which the semiconductor substrate is intended to be doped. This may be done by filing the trench with a solid form of the dopant to the height of the trench intended to be doped. For example, a trench is firstly filled completely with arsenic glass and the filling is subsequently etched back as far as a depth below which the semiconductor is intended to be doped. Afterward, the semiconductor substrate is heated, so that the arsenic diffuses from the arsenic glass into the surrounding semiconductor. With decreasing dimensions of the trenches, however, a sufficient quantity of dopant cannot be made available by use of arsenic glass. Furthermore, as a result of the depletion of the arsenic glass during the doping operation, as the duration of the heat treatment steps increase, the maximum of the dopant concentration migrates away from the trench wall into the semiconductor.
In order to achieve a sufficiently high doping even in trenches of small dimensions, efforts are shifting to introducing the dopant from the gas phase into the semiconductor. Since a sufficiently high concentration of the dopant is continuously available in the gas phase, a high doping of the sections of the semiconductor which form the bottom electrode in the finished capacitor can be achieved, since it is possible to set a high concentration of the dopant in particular at the interface between semiconductor and dielectric. However, this requires that those regions of the semiconductor which are intended to remain undoped are covered with a diffusion barrier.
During the fabrication of deep trench capacitors, firstly a collar made of silicon nitride is constructed in the upper section of the trench, to act as a diffusion barrier during the gas phase doping. To that end, the trench may, for example, firstly be filled with polysilicon, which is subsequently etched back isotropically as far as the lower edge of the collar to be fabricated. Afterward, a thin layer made of silicon nitride is deposited on the uncovered walls in the upper section of the trench. This ceramic material is generally deposited by a Chemical Vapor Deposition (CVD) or an Atomic Layer Deposition (ALD) method. Afterward, the silicon nitride layer deposited on the polysilicon filling is etched back anistropically, so that the silicon nitride layer only remains at the trench walls arranged perpendicular to the top side of the substrate and forms a collar there. As a result of the etching back of the silicon nitride layer, the top side of the filling made of polysilicon is uncovered again. The polysilicon is subsequently removed, thereby obtaining the original trench again, with a collar arranged at the upper termination of the trenchwall adjacent to the opening of the trench with respect to the top side of the substrate. The uncovered substrate walls can then be doped by gas phase doping. Such a construction of a trench capacitor is also referred to as a “collar first” concept.
In the above procedure, difficulties arise when removing the filling made of polysilicon. On the one hand, it is desirable to remove the filling completely; on the other hand, however, the semiconductor substrate surrounding the filling should remain undamaged during the removal of the filling. To date, the problem has been solved by the trench firstly being completely lined with an etching stop layer, for example with a layer made of Si3N4. After the construction of the oxide collar, the polysilicon filling is then removed in a first step. In a second step, the etching stop layer is removed by etching the silicon nitride with aqueous phosphoric acid, for example. The selectivity between etching stop layer and the material of the collar is problematic in this case. The conditions for the removal of the etching stop layer therefore have to be controlled very precisely.
During chemical vapor deposition, a ceramic layer is fabricated in such a way that gaseous precursor compounds are fed to a substrate surface and said precursor compounds are deposited to form the ceramic material forming the ceramic layer. The precursor compound contains at least one element that is incorporated in the ceramic material, as well as reactive groups that enable a reaction with a further precursor compound. These groups may dissociate, for example, and the element contained in the precursor compound may be converted into the ceramic material. Chemical vapor deposition can essentially be carried out in two ways. In the first method, the precursor compounds of all the elements contained in the ceramic material are fed to the substrate surface simultaneously. The precursor compounds then react with one another at the substrate surface, and the ceramic material is deposited on the substrate surface. Layer thicknesses of up to a many micrometers can be produced in a relative short time by this method. However, difficulties may be caused by flow fluctuations in the reaction space, which lead to fluctuations in the thickness of the deposited layer. In order to achieve a layer thickness that is as uniform as possible, therefore, the reaction that proceeds during vapor deposition has been divided into a plurality of substeps.
In the ALD method, only a precursor compound of one element is adsorbed on the substrate surface to form a monomolecular layer. Generally, reactive groups are provided on the substrate surface, converting the precursor compound and irreversibly binding it in the process. The advantage of the ALD method is that it proceeds in self-limiting fashion, so that fluctuations in the process conditions do not lead to fluctuations in the thickness of the layer deposited on the substrate. The synthesis of a ceramic layer from monolayers results in a very time-consuming process. Furthermore, formation of a monomolecular layer should be as complete as possible in each case. In order to obtain a high conversion, and thus a high homogeneity of the layer, precursor compounds are therefore usually deposited at a relatively high temperature, generally at temperatures above 300° C.
In order to keep the thermal loading as low as possible during the fabrication of semiconductor elements, various low temperature ALD methods have been developed. These methods, employed at temperatures in the region of room temperature, enable deposition rates that achieved only at temperatures above 300° C. in previously used ALD methods.
In one low temperature ALD method, deposition of the precursor compounds is carried out under the action of a plasma. In this case, a portion of the molecules of at least one of the precursor compounds is converted with the aid of a plasma to form radicals having a very high reactivity. At as low a temperature as room temperature, the radicals react very rapidly with groups that are provided to the substrate surface. Such a method is described for example in U.S. Pat. No. 6,342,277 B1.
Another low temperature ALD method utilizes a catalyst in order to enable the deposition of the precursor compound to proceed at sufficiently high speed at as low a temperature as room temperature. In the latter method, although the catalyst participates in the deposition reaction, it does not itself undergo any change through the reaction. Such a method is described for example by J. W. Klaus, O. Sneh, A. W. Ott and S. M. George, Surface Review & Letters (1999), 435–448. In order to construct a ceramic layer comprising silicon dioxide, a small portion of pyridine is in each case added to the precursor compounds SiCl4 and H2O. Through the catalytic effect of the pyridine, the deposition of the precursor compounds proceeds at sufficiently high speed even at temperatures in the region of room temperature.
A further development of this method is reported by J.-E. Park, J.-H. Ku, J.-W. Lee, J.-H. Yang, K.-S. Chu, S.-H. Lee, M.-H. Park, N.-I. Lee, H.-K. Kang and K.-P. Suh (IEEE 2002). The latter report describes the use of Si2Cl6 (HCD) as silicon-containing precursor compound. Pyridine is likewise used as catalyst, and water as precursor compound for oxygen. In the above process, uniform layers of high quality can be fabricated at high deposition rates. Changes shown from here on.